FIG. 1 shows the structure of a circuit for one pixel section (pixel circuit) of a basic active organic EL display device, and FIG. 2 shows one example of the structure of a display panel, and signals input to the display panel.
As shown in FIG. 2, a pixel data signal, a horizontal sync signal, a pixel clock and other drive signals are supplied to a source driver 10. Also, the horizontal sync signal, a vertical sync signal and other drive signals are supplied to a gate driver 12. Vertical direction data lines Data extend from the source driver 10 to each column of the pixel section 14, while horizontal direction gate lines Gate extend from the gate driver 12 to each row of the pixel section 14.
As shown in FIG. 1, a pixel circuit includes a selection TFT 2 having a source or a drain connected to a data line Data and a gate connected to a gate line Gate, a drive TFT 1 with the drain or source of the selection TFT 2 connected to a gate, and a source connected to a power supply PVdd, a storage capacitor C connected across the gate and source of the drive TFT 1, and an organic EL element 3 having an anode connected to the drain of the drive TFT 1, and a cathode connected to a low voltage power supply CV.
A data signal is stored in the storage capacitor C by setting a gate line (Gate), that extends in the horizontal direction, to a high level to turn the selection TFT 2 on, and in this state placing a data signal having a voltage corresponding to a display brightness on a data line (Data) that extends in the vertical direction. In this way, the drive TFT 1 supplies a drive current corresponding to the data signal stored in the storage capacitor C to the organic EL element 3, and the organic EL element 3 emits light.
Here the amount of light emission and current of the organic EL element 3 are in a substantially proportional relationship. Normally, a voltage (Vth) is supplied across the gate of the drive TFT 1 and PVdd such that a drain current approaching that for a black level of the pixel starts to flow. Also, the amplitude of the image data signal is an amplitude so as to give a prescribed brightness close to a white level. Specifically, a voltage supplied to the data line Data is controlled using the image data signal so that a current flows in the organic EL element 3 in a range from a black level to a white level.
An image signal formed from data of a plurality of bits (for example 8 bits) for each pixel section 14, a horizontal sync signal (HD) indicating the end of 1 line, a pixel clock indicating the end of data for each pixel of the image data signal, a vertical sync signal (VD) indicating the end of each frame, and other drive signals are input to the display panel. An image data signal, horizontal sync signal, pixel clock and other drive signals are input to the source driver 10, and image data signals corresponding to data line Data that has been set for each pixel column are sequentially supplied to the source driver 10. Also, a horizontal sync signal, vertical sync signal and other drive signals are input to the gate driver 12, and a gate line Gate of a corresponding row is selected at the timing for supplying image data signals for pixels of each row from the source driver 10 to the data line Data. In this way, image data signals for each pixel section 14 are written to that pixel section 14, and display is carried out.
FIG. 3 shows a relationship for CV current (corresponding to brightness) flowing in the organic EL element 3 with respect to input signal voltage (voltage of the data line Data (data voltage)) of the drive TFT 1. It is possible to carry out appropriate gradation control for the organic EL element 3 by determining the image data signal so that Vb is supplied as the black level voltage and Vw is supplied as the white level voltage.
In this manner, the input signal voltage of the pixel, and the current flowing in the organic EL element 3 of that pixel, are not in a proportional relationship. Therefore, as shown in FIG. 4, RGB signals rn, gn and bn for every pixel, being the image data signal that is input, are input to three corresponding gamma correction circuits (γLUT) 16, and here a relationship between the image data signal and the brightness is made linear. In FIG. 4, the RGB image data signals rn, gn and bn are corrected using respective look-up table type gamma correction circuits (γLUT) 16. Corrected image data signals Rn, Gn and Bn are input to the source driver 10. In FIG. 4, the source driver 10 is formed using a shift register 10a and a data latch and D/A 10b. Specifically, image data signals are sequentially input to the shift register 10a of the source driver 10, synchronously converted to an analog signal in the data latch and D/A 10b once there is image data for one horizontal line, and supplied to the data line Data. In the display panel 18, regions where display is carried out are shown as the display panel (effective pixel region) 18.
Here, in the pixel circuit of FIG. 1 stray capacitance and resistance components accompanying wiring are not shown, but in actual fact these cannot be disregarded with respect to the characteristics and are formed as distributed constant circuits. As shown in FIG. 2, a plurality of pixel sections 14 are connected to a PVDD line for supplying power supply voltage to each pixel, and so if there is a resistance component there will be variation in the voltage of the source of the transistor (drive TFT 1) for driving the organic EL element, according to the magnitude of the current of other pixels. That is, as current of pixels that are connected to the same PVDD line increases, lowering of voltage will increase. If the selection TFT 2 is turned ON and there is a lowering of the source voltage during writing of a Data voltage to the storage capacitor C, an absolute value of Vgs will drop, which shows that pixel current is reduced and emission brightness is lowered, and as a result it is difficult to perform display in accordance with Data voltage.
In order to solve this problem, in U.S. Patent Application Publication No. 2007/0128583 a transistor for turning off current for pixels while writing is added, and voltage drop for horizontal lines is prevented.
As described above, due to current flowing in power supply lines, which have a resistance component, power supply voltage for the pixel circuit drops, and the display brightness becomes non-uniform. For example, if a white image is displayed over the whole of a panel having power supply lines arranged, as shown in FIG. 6, power supply voltage drop occurs with the distribution shown in the drawing. In particular, in the case where a white window pattern is displayed on a grey background, as shown in FIG. 5, as the left and right (sections b and c) of the window approach the window they become darker than other background sections (sections d and e), and boundaries with other sections are conspicuous.
With U.S. Pat. No. 6,943,501 and JP 2003-027999A, it is assumed that it is possible to ignore the resistance of vertical direction power supply lines on one or both sides of a panel, and power supply lines are drawn out in a horizontal scanning direction parallel to the pixels, and voltage lowering due to resistance of power supply lines in this horizontal direction is obtained by calculation, to correct input data. In the event that left and right vertical direction power supply lines are formed on an array substrate forming the panel, it is necessary to broaden the width in order to lower resistance, which affects the external width of the panel. Also, in the case where it is not possible to ensure sufficient width, voltage drop in the y-y′ direction in FIG. 6 occurs, and brightness becomes non-uniform in the vertical direction.